Semiconductor package using terminals formed on a conductive layer of a circuit board

ABSTRACT

A small package is provided for a flash EEPROM memory. The small package uses terminals which are part of a bottom conductive layer of a circuit board. In this manner, the final package can be quite thin. The circuit board can be connected to the integrated circuits and passive devices and can be encapsulated in plastic or glued to a plastic cover. In this manner, a thin and relatively inexpensive package can be formed. Additionally, the circuit board can have testing connections which can be removed before forming the final package.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 11/021,169,filed Dec. 21, 2004; which application is a continuation of applicationSer. No. 09/866,022, filed May 24, 2001, now U.S. Pat. No. 6,867,485;which application is a continuation of application Ser. No. 09/487,106,filed Jan. 19, 2000, now U.S. Pat. No. 6,410,355; which application is adivisional of application Ser. No. 09/096,140, filed Jun. 11, 1998, nowU.S. Pat. No. 6,040,622. These applications are incorporated byreference as if fully set forth herein.

FIELD OF THE INVENTION

The present invention relates to the packaging of semiconductorintegrated circuits. In particular, the system relates to the packagingof memory chips

BACKGROUND OF THE INVENTION

In recent years, flash Electrically Erasable Programmable Read-OnlyMemory (EEPROM) has become popular. Flash EEPROMs are a high-density,nonvolatile memory.

This flash EEPROM package contains multiple integrated circuits,including a controller chip and a memory chip. The flash memory packagesalso require capacitors for charge pumping so that the requiredprogramming voltage can be obtained from a lower circuit voltage.

It is desired to have a smaller, thinner memory package format to beused with digital cameras and the like.

SUMMARY OF INVENTION

In order to have a small package, the system of the present inventionputs the integrated circuits onto a circuit board or PC board, where aconductive layer of the circuit board forms the terminals for thepackage. This conductive layer of the circuit board is positioned on theoutside of the package. In this way, a very thin package can beproduced. No additional connections are required from the circuit boardto terminals.

In one preferred embodiment, the circuit board with the integratedcircuits and passive devices can be placed in a mold and encapsulated inplastic with the terminal side of the circuit board exposed. Before theencapsulating process, the integrated circuits used in the package canbe covered with an epoxy material or with another type of plastic forprotection. Alternately, the circuit board with the integrated circuitsand passive devices can be glued into a plastic case or overmolded.

Another embodiment of the present invention concerns a testingconnection region of the circuit board. At one end of the circuit board,testing connections allow access to the integrated circuits for burn-intesting the integrated circuits and allow the programming of theintegrated circuits so as to avoid bad memory cells. The testingconnection region of the circuit board material is cut away beforepackaging so that the final package can have a smaller form.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an actual-size bottom view of the package of the presentinvention.

FIG. 2 is an enlarged perspective view of the package of the presentinvention.

FIGS. 3A and 3B are enlarged front and back views of the circuit boardmaterial for use in the package of the present invention.

FIG. 4 is a top view of the circuit board with integrated circuits andpassive devices.

FIG. 5 illustrates the circuit board with integrated circuits andpassive devices with the testing connection region removed.

FIG. 6 is an exploded cross-sectional diagram of a prior art circuitboard material.

FIG. 7A is a cross-sectional view of a mold for use with the package ofthe present invention.

FIG. 7B is a perspective view showing the top portion of the mold ofFIG. 7A.

FIG. 7C is a perspective view showing the bottom portion of the mold ofFIG. 7A.

FIG. 8A is a cross-sectional view of a package of the present inventionhaving a frame.

FIG. 8B is a top view of a package of FIG. 8A.

FIG. 8C is a bottom view of a package of FIG. 8A.

FIG. 9 is a cross-sectional view of an alternate embodiment of thepresent invention in which the circuit board is glued into a plasticcover.

FIG. 10 is a top view of the circuit board with protective materialaround the integrated circuits.

FIG. 11 is a top view of an alternate embodiment showing the circuitboard with protective material around the integrated circuits.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a bottom view of a package 20 of the present invention. Thepackage 20 is shown with terminals 22 which, as described below, arepart of a circuit board. FIG. 1 shows the actual size of a preferredembodiment. The package in the preferred embodiment is 1¼ inches long by⅞ of an inch wide. In the preferred embodiment, the thickness of thepackage is preferably 12 mils or less. Such a small-sized package can beadvantageously used with systems such as digital cameras in which sizeis a factor. FIG. 2 is a perspective view of the package which is shownenlarged.

FIG. 3A is an enlarged top view of a circuit board 24 for use with thepackage of the present invention. The circuit board 24 includes a numberof conductive traces 26 which interconnect the integrated circuits andpassive devices once they are placed on the circuit board 24. Connectingregions 25 are provided so that leads from the integrated circuits canbe connected to the circuit board by conventional wire bonding.

Testing connections 28 are also provided interconnected to theintegrated circuits. As is described below, the testing connections 28can be used for burn-in testing and memory mapping the devices. Thetesting connections 28 are removed after testing to make the finalpackage size smaller.

FIG. 3B shows the back side of the circuit board. Note that in thepreferred embodiment, the back side of the circuit board material onlycontains the terminals 30. This allows the circuit board to be exposedon the outside of the package. The visual effect of the package isimproved and the problem of inadvertent electrical connections to thepackage is reduced. The terminals 30 are connected by vias to theintegrated circuits. The terminals 30 allow for the reading and writingof data from the flash EEPROM package. Note that the terminals are notat the edge of the package but on one of the sides.

FIG. 6 illustrates the construction of a prior art circuit board. Asshown in FIG. 6, in a preferred embodiment, the circuit board is a PCboard comprising two sections, 40 and 42. Section 40 comprises aninsulating layer 40 a with conductive layers 40 b and 40 c, formedthereupon. These layers are patterned so as to interconnect thedifferent devices on the PC board. Connections between layers such aslayers 40 b and 40 c can be made by conductive vias, such as the vias 44or 46. Similarly, the section 42 comprises an insulating layer 42 a andconductive layers 42 b and 42 c. In the preferred embodiment, layer 42 cis patterned to form the terminals with no other conductive traces onthat layer. Sections 40 and 42 can be connected by a thin glue layer.The PC board materials can be quite thin; in one preferred embodiment,the PC board material is 3 mils thick or less.

FIG. 4 shows integrated circuits 50 and 52, placed on the circuit board24. The integrated circuits 50 and 52 are glued onto the circuit boardand, as described above, wire bond connections are made from the diebond pads to the regions 25. In a preferred embodiment, integratedcircuit 52 is a controller chip and integrated circuit 50 is a mainmemory chip. Passive devices are also connected to the circuit board.For example, charge-pumping capacitors are used to convert the suppliedvoltage to the larger voltage required to modify the flash EEPROM. Inone preferred embodiment, the capacitors can convert a 2.6 volt suppliedvoltage into the required 11 volts. As described above, once theintegrated circuits and passive devices are connected, the testingconnection region 28 can be used for the testing and memory mapping ofthe EEPROM circuitry. Note that the testing connection region 28 canhave a greater number of contacts than the package terminals. In theembodiment shown, there are seven terminals in the final package andtwenty-six contacts used for the testing connection region. In apreferred embodiment, the burn-in testing involves the operation of theunit at relatively high voltages. After burn-in testing, defectivememory cells are mapped-out. As shown in FIG. 5, the test connectionregion 28 is cut-off after the burn-in testing and memory mapping havebeen done. This allows for a smaller final package.

FIGS. 7A-7C illustrate the injection molding of the circuit board withassociated integrated circuits and passive devices into a package. Thecircuit board 62 with the attached integrated circuit 64 is vacuumclamped to the top portion 66 of the injection mold 60. The bottomportion 68 of the injection mold is attached to the top portion 66 andplastic materials under heat and pressure are injected into the mold tosurround the top and sides of the circuit board 62 and integratedcircuit 64. In a preferred embodiment, the plastic material is a thermalplastic or a thermal setting plastic. The plastic is injected throughthe ports 70. The clamping of the bottom of the circuit board 62 to thetop portion 66 prevents the terminals of the package from being coatedwith the injected plastic material. FIG. 7B shows the top portion 66 ofthe clamp. FIG. 7C shows the bottom portion 68 of the clamp. Note thatthe bottom portion 68 allows for a region 72 in which a label can bepositioned so that the final package includes a label.

The use of a circuit board with the injection molding process has anumber of advantages. The circuit board material allows for theinterconnection of more than one integrated circuit on the multipleconnective layers. It also allows for the dedication of one conductivelayer for terminals.

FIG. 8A is a cross-sectional view of a modified injection moldedembodiment. This modified injection molded embodiment produces a package76 having a plastic frame 78. The circuit board 62 and integratedcircuit 64 are positioned on the frame 78 and an injection moldedplastic material 80 added. In a preferred embodiment, the frame 78includes a projection 78 a which helps the injection plastic material 80attach to the frame 78. FIG. 8B shows a top view of the package of theembodiment of FIG. 8A. FIG. 8C shows the bottom view of the package ofthe embodiment of FIG. 8A.

In an alternate embodiment, a plastic cover 82 can be glued to thecircuit board material 62 and integrated circuit 64 using an epoxy 84.The injection molding methods have some advantages over this alternateembodiment since they do not require processing by hand. Additionally,the plastic molded package will be more durable and corrosion resistantthan the glued package. However, both methods allow for an inexpensivepackage.

Looking again at FIG. 7A, in a preferred embodiment, the integratedcircuits 64 will be isolated by a protective material from therelatively hot plastic injection molding material. In one embodiment,the integrated circuits are protected by an epoxy coating.

FIGS. 10 and 11 show an alternate embodiment in which the integratedcircuits 50 and 52 are protected by a first plastic encapsulating step.The first plastic encapsulating step can preferably be a transfer doneat lower temperatures than the injection molding. This will protect theintegrated circuits 50 and 52 from temperature and stress. The transfermolded plastic 86 need not cover the passive devices 51 which areallowed to contact the higher temperature plastic. Note that in theembodiment of FIG. 11, there is a narrow region 88 a of the transfermolded plastic 88 surrounding the integrated circuits. This narrowregion 88 a is used to reduce the stress between the integratedcircuits.

Various details of the implementation and method are merely illustrativeof the invention. It will be understood that various changes in suchdetails may be within the scope of the invention, which is to beeliminated only by the appending claims.

1. A package including: a circuit board; a set of circuit elements onthe circuit board, the set of circuit elements including at least oneintegrated circuit and passive components; and packaging materialsurrounding the set of circuit elements and part of the circuit board,wherein one side of the circuit board includes a set of terminals thatare visible from the side of the package, the set of terminals beingpositioned away from the edge of the circuit board.
 2. The package ofclaim 1, wherein the packaging material includes molded plastic.
 3. Thepackage of claim 2, wherein the packaging material includes a borderingframe.
 4. The package of claim 1, wherein one side of the circuit boardis exposed.
 5. The package of claim 4, wherein the exposed side of thecircuit board material includes the set of terminals connected to theremainder of the circuit board by vias.
 6. The package of claim 5,wherein the circuit board material is attached to the packaging materialby epoxy.
 7. The package of claim 1, wherein the circuit elementsinclude at least two integrated circuits and passive devices.
 8. Thepackage of claim 7, wherein the thickness of the package is less than 12mils.
 9. The package of claim 1, wherein the package is a flash EEPROMpackage.
 10. A package including: a circuit board; at least oneintegrated circuit on the circuit board; and packaging materialsurrounding the set of circuit elements and part of the circuit board,wherein one side of the circuit board is exposed, the exposed side ofthe circuit board material including a set of terminals connected to theremainder of the circuit board by vias.
 11. The package of claim 10,wherein the circuit board material is attached to the packaging materialby epoxy.
 12. The package of claim 10, wherein on the exposed side ofthe circuit board only the set of terminals is exposed.
 13. The packageof claim 10, wherein the circuit elements include at least twointegrated circuits and passive devices.
 14. The package of claim 10,wherein the thickness of the package is less than 12 mils.
 15. Thepackage of claim 10, wherein the package is a flash EEPROM package. 16.A package including: a circuit board; a set of circuit elements on thecircuit board, the set of circuit elements including at least oneintegrated circuit and passive components; and a plastic materialencasing the set of circuit elements and part of the circuit board,wherein one side of the circuit board includes a set of terminals thatare accessible from the side of the package, the set of terminals beingpositioned away from the edge of the circuit board.
 17. The package ofclaim 16, wherein one side of the circuit board is exposed.
 18. Thepackage of claim 17, wherein the exposed side of the circuit boardmaterial includes the set of terminals connected to the remainder of thecircuit board by vias.
 19. The package of claim 16, wherein the circuitboard material is attached to the packaging material by epoxy.
 20. Thepackage of claim 16, wherein on the exposed side of the circuit boardonly the set of terminals is exposed.